Analog Devices Inc. AD6684 135MHz Quad IF Receivers

Analog Devices Inc. AD6684 135MHz Quad IF Receivers consists of four 14-bit, 500MSPS ADCs and multiple digital processing blocks. The digital processing blocks include four wideband DDCs, an NSR, and VDR monitoring. 

The quad ADC cores use a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. Users can operate the AD6684 Receivers in DDC, NSR, and VDR modes via SPI-programmable profiles. Each pair of ADC data outputs connects to two DDCs using a crossbar mux. Each DDC consists of up to five cascaded signal processing stages, including a 48-bit frequency translator, NCO, and up to four half-band decimation filters. The ADC outputs connect to an NSR block. AD6684's integrated NSR circuitry delivers improved SNR performance in a smaller frequency band within the Nyquist bandwidth while maintaining a 9-bit output resolution. 

In addition, users can configure each pair of IF receiver outputs to either one or two lanes of Subclass 1 JESD204B-based high-speed serialized outputs. SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins support multiple device synchronization. 

Analog Devices Inc. AD6684’s on-chip buffer and a sample-and-hold circuit enable low-power operation, small size, and ease-of-use. The overall design of the AD6684 135MHz Quad IF Receivers makes the devices well suited for communications applications with sampling analog signals up to 1.4GHz.


  • JESD204B (Subclass 1) coded serial digital outputsLane rates up to 15Gbps
  • 1.68W total power at 500MSPS420mW per analog-to-digital converter (ADC) channel
  • SFDR = 82dBFS at 305MHz (1.8Vp-p input range)
  • SNR = 66.8dBFS at 305MHz (1.8Vp-p input range)
  • Noise density = −151.5dBFS/Hz (1.8Vp-p input range)
  • Analog input buffer
  • On-chip dithering to improve small-signal linearity
  • Flexible differential input range 1.44Vp-p to 2.16Vp-p (1.80Vp-p nominal)
  • 82dB channel isolation/crosstalk
  • 0.975V, 1.8V, and 2.5V DC supply operation
  • Noise shaping requantizer (NSR) option for the main receiver
  • Variable dynamic range (VDR) option for digital pre-distortion (DPD)
  • Four integrated wideband digital downconverters (DDCs)48-bit numerically controlled oscillator (NCO), up to 4 cascaded half-band filters
  • 1.4GHz analog input full power bandwidth
  • Amplitude detects bits for efficient automatic gain control (AGC) implementation
  • Differential clock input
  • Integer clock divided by 1, 2, 4, or 8
  • On-chip temperature diode
  • Flexible JESD204B lane configuration


  • Communications
  • Diverse multiband, multimode digital receivers
  • 3G/4G, W-CDMA, GSM, LTE, LTE-A
  • HFC digital reverse path receivers
  • Digital pre-distortion observation paths
  • General-purpose software radios

Functional Block Diagram

Block Diagram - Analog Devices Inc. AD6684 135MHz Quad IF Receivers
Published: 2017-07-31 | Updated: 2022-04-18