Analog Devices Inc. ADF4196 Fractional-N PLLs Frequency Synthesizers
Analog Devices Inc. ADF4196 Fractional-N PLLs Frequency Synthesizers implement local oscillators (LO) in the up-conversion and down-conversion sections of wireless transmitters and receivers. The ADF4196 design meets the GSM/EDGE lock-time requirements for base stations. The fast settling capability makes the ADF4196 well-suited for pulse-Doppler radar applications. The design includes a low-noise, digital phase frequency detector (PFD) and a precision differential charge pump. Analog Devices ADF419's differential amplifier converts the output of the differential charge pump to a single-ended voltage for the external voltage-controlled oscillator (VCO). The sigma-delta (Σ-Δ) based fractional interpolator, in conjunction with the N divider, enables programmable modulus, fractional-N division. Designers can implement a complete phase-locked loop (PLL) if the synthesizer is used with a VCO and an external loop filter.
The ADF419 features a switching architecture that ensures that the PLL settles within the GSM time-slot guard period. This switching architecture eliminates the need for a second PLL and associated isolation switches. As a result, the fractional-N PLL architecture decreases the complexity, PCB area, shielding, and characterization compared to previous ping-pong GSM PLL architectures.
Features
- Fast settling, fractional-N PLL architecture
- Single PLL replaces ping-pong synthesizers
- Frequency hop across GSM band in 5μs with phase settled within 20μs
- 1 degree rms phase error at 4GHz RF output
- Digitally programmable output phase
- RF input range up to 6GHz
- 3-wire serial interface
- On-chip, low-noise differential amplifier
- −216dBc/Hz phase noise figure of merit
Applications
- GSM/EDGE base stations
- PHS base stations
- Pulse-Doppler radar
- Instrumentation and test equipment
- Beam-forming/phased array systems
Functional Block Diagram
Published: 2017-02-24
| Updated: 2022-03-11