Analog Devices Inc. ADRF5545A RF Front-End Multichip Module

Analog Devices ADRF5545A Dual-Channel RF Front-End Multichip Module is designed for time-division duplexing (TDD) applications that operate from 2.4GHz to 4.2GHz. The ADRF5545A is configured in dual channels with a cascading two-stage low noise amplifier (LNA) and a high power silicon single-pole, double-throw (SPDT) switch.

In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure (NF) of 1.45dB and a high gain of 32dB at 3.6GHz with an output third-order intercept point (OIP3) of 32dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 16dB of gain at a lower current of 36mA. In power-down mode, the LNAs are turned off and the device draws 12mA.

In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.65dB. The device handles long-term evolution (LTE) average power (9dB peak to average ratio (PAR)) of 40dBm for full lifetime operation and 43dBm for single event (<10 sec) LNA protection operation


  • Integrated dual-channel RF front end
    • 2-stage LNA and high power SPDT switch
    • On-chip bias and matching
    • Single supply operation
  • Gain
    • High gain mode: 32dB typical at 3.6GHz
    • Low gain mode: 16dB typical at 3.6GHz
  • Low noise figure
    • High gain mode: 1.45dB typical at 3.6GHz
    • Low gain mode: 1.45dB typical at 3.6GHz
  • High isolation
    • RXOUT-CHA and RXOUT-CHB: 47dB typical
    • TERM-CHA and TERM-CHB: 52dB typical
  • Low insertion loss: 0.65dB typical at 3.6GHz
  • High power handling at TCASE = 105°C
    • Full lifetime
      • LTE average power (9dB PAR): 40dBm
    • A single event (< 10-sec operation)
      • LTE average power (9dB PAR): 43dBm
  • High OIP3: 32dBm typical
  • Power-down mode and low gain mode for LNA
  • Low supply current
    • High gain mode: 86mA typical at 5V
    • Low gain mode: 36mA typical at 5V
    • Power-down mode: 12mA typical at 5V
  • Positive logic control
  • 6mm×6mm, 40-lead LFCSP package


  • Wireless infrastructure
  • TDD massive multiple input and multiple output and active antenna systems
  • TDD-based communication systems

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Functional Block Diagram

Block Diagram - Analog Devices Inc. ADRF5545A RF Front-End Multichip Module
Published: 2019-10-02 | Updated: 2022-03-11