Analog Devices Inc. LTC695x Ultra-low Jitter Clock Synthesizers

Analog Devices Inc. LTC695x Ultra-low Jitter Clock Synthesizers offer designers clocking solutions that help maximize the data converter signal-to-noise ratio (SNR). The LTC695x Ultra-low Jitter Clock Synthesizers are easily synchronized using the Analog Devices synchronization programs. The EZSync™ multi-chip synchronization ensures consistent edge alignment across all outputs. ParallelSync™ multi-chip parallel synchronization allows designers to re-time the outputs of multiple ICs to the common reference clock. This process enables reference-aligned synchronization in the reference clock domain with an easy-to-meet nanosecond range setup and holds time requirements.

Features

LTC6950
- Additive jitter <90fsRMS(10Hz to Nyquist frequency)
- 1.4GHz maximum frequency
- Programmable 1 to 63 output dividers
- Programmable 0 to 63 clock cycle delay
- EZSync multichip clock edge synchronization
- –226dBc/Hz normalized in-band phase noise floor
- –274dBc/Hz normalized 1/f phase noise
LTC6951
- Output Jitter
  - 90fsRMS (12kHz to 20MHz)
  - 115fsRMS (ADC SNR Method)
- –165dBc/Hz at 250MHz noise floor
- EZSync, ParallelSync Multichip Synchronization
- SYSREF generation for JESD204B, Subclass 1
- 1.95MHz to 2.7GHz output frequency range
- –229dBc/Hz normalized in-band phase noise floor
- –277dBc/Hz normalized in-band 1/f noise
- Five independent, low noise outputs
- Reference input frequency up to 425MHz
LTC6952
- JESD204B/C, Subclass 1 SYSREF signal generation
- Low noise integer-N PLL
- Additive output fitter <6fsRMS
  - (Integration BW = 12kHz to 20MHz, f = 4.5GHz)
- Additive output jitter 65fsRMS (ADC SNR method)
- EZSync, ParallelSync multichip synchronization
- –229dBc/Hz normalized in-band phase noise floor
- –281dBc/Hz normalized in-band 1/f noise
- Eleven independent, low noise outputs with programmable coarse digital and fine analog delays
- Flexible outputs can serve as either a device clock or SYSREF signal
- Reference input frequency up to 500MHz
- LTC6952Wizard™ software design tool support
- –40ºC to +125°C operating temperature range

LTC6953
- JESD204B/JESD204C, Subclass 1 SYSREF signal generation
- Additive Output Jitter
  - <6fsRMS (Integration BW = 12kHz to 20MHz, f = 4.5GHz)
  - 65fsRMS (ADC SNR method)
- EZSync, ParallelSync multichip synchronization
- Eleven independent, low noise outputs with programmable coarse digital and fine analog delays
- Flexible outputs can serve as either a device clock or SYSREF signal
- LTC6952Wizard software design tool support
- –40°C to +125°C operating junction temperature range
LTC6954
- Three independent, low noise outputs
- Up to 1.8GHz maximum input frequency
- EZSync clock synchronization compatible
- Clock dividers covering all integers from 1 to 63
- Phase delays covering all integers from 0 to 63
- –40°C to +105°C junction temperature range
LTC6955
- 11 output buffer (TC6955)
- 10 buffered outputs and one ÷2 output (LTC6955-1)
- Additive output jitter ~45fs RMS (ADC SNR Method)
  Additive output jitter < 5fs RMS
  - (Integration BW = 12kHz to 20MHz, f = 7.5GHz)
- Eleven ultralow noise CML outputs
- Parallel control for multiple output configurations
- –40°C to +125°C operating junction temperature range